Junior ASIC Engineer (Intern)

Hybrid (2 days onsite) in Canada, Vancouver

8-month term effective May 2025.

Corporate Introduction

As a founding premier member of RISC-V International, Andes is the leading supplier and technological innovator in the RISC-V market with a wide range of processor products fulfilling performance/area/power requirements. Andes has perfected the technology of quick and efficient design of custom extensions to its proprietary CPU. With over 10 billion cumulative shipments of SoCs embedded with Andes CPU IP, Andes products have covered audio, Bluetooth, gaming, GPS, machine learning, MCU and more. Our design innovation enables us to quickly adapt to the rapidly evolving demands of RISC-V customers.

Founded in 2005, Andes yearly revenue has tripled in size from $10 million in 2017 to $30 million in 2021. Andes was ranked among "100 Fastest-Growing Companies" in 2020 by CommonWealth Magazine. Headquartered in Taiwan, Andes is capitalizing on its current growth by branching out its offices to the US and Canada to expand on its current 300 employee workforce. Employees are valued as the key ingredient to the success of the company. They will have an opportunity to create a strong and positive impact on the company, where feedback is encouraged and implemented.

Home Page

http://www.andestech.com/en/homepage/

Role

You will be a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.

As a junior member of this team, you will have the unique opportunity to learn from veterans of the CPU industry. You will be exposed to multiple phases of the hardware ASIC IP development from concept through design and verification. Initially, you will develop scripts to automate various aspects of our R&D environment. Next, you will be taught RISCV architecture concepts and finally you will be assigned an Andes IP or submodule and be tasked to verify it fully.

Position Overview

We seek undergraduate or graduate Co-op students to join our VLSI team for, preferably, 8-month term effective May 2025.

Daily activities include:

Communication with peers to discuss technical details
Verification regression, triage, and functional bug analysis; Create verification tests and constructs that help validate the functionality of designs
Develop scripts and flows to automate the verification, synthesis and report generation
Technical documentation

Technical Requirements

Have studied or completed courses in VLSI / ASIC hardware / digital design, CPU architecture, digital systems, assembly language programming or computer sciences
Have strong communication skills and a team-player attitude
Have some domain knowledge of verification techniques and/or digital hardware design concepts
Have experience, knowledge or strong interest in CPU architecture and assembly languages
Have experience or knowledge using Verilog, System Verilog
Have experience or knowledge using Unix and scripting languages such as make, shell, perl or python
Have experience or knowledge of using version control software such as CVS, Git, Perforce

Desirable Skills

Strong desire to learn and willing to devote extra effort to achieve perfection
Strong team player and possess a positive attitude

Number of Positions

Work Terms

40 hours per week, Monday through Friday

Andes Technology Corporation

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Junior ASIC Engineer (Intern)